SystemVerilog: Difference between `logic` and `reg`

In SystemVerilog, `logic` and `reg` are both data types used for representing signals, but they have some key differences:

1. logic:
   `logic` is a 4-state data type that can take on the values 0, 1, X (unknown), and Z (high impedance). It is commonly used for modeling digital signals in RTL (Register Transfer Level) code.
2. reg:
   `reg` is a 2-state data type that can take on the values 0 and 1. It is used to represent storage elements like registers and memories.

Overall, `logic` is more versatile and commonly used for handling digital signals, while `reg` is more specific to storage elements in SystemVerilog.