SystemVerilog Interview Question: Difference between always_comb and always_latch

In SystemVerilog, always_comb and always_latch are similar in that they are both used to describe combinational logic in a design. However, there are key differences between them:

• always_comb: The always_comb block is used to describe combinational logic that does not have any state storage elements, such as flip-flops. It is used for purely combinational logic that is directly derived from its input signals.
• always_latch: The always_latch block is used to describe latch-based logic. Latches are level-sensitive storage elements that can propagate their inputs to their outputs whenever the latch enable signal is active. They are not recommended for general use in design due to potential race conditions and sensitivity to glitches.

Therefore, the main difference between always_comb and always_latch in SystemVerilog is that always_comb is used for pure combinational logic without storage elements, while always_latch is used for latch-based storage elements.