How do you differentiate between initial and final blocks in SystemVerilog?

In SystemVerilog, initial and final blocks are used for different purposes:

• Initial Blocks: Initial blocks are used for initializing variables and executing code at the beginning of the simulation. They are executed only once at the start of the simulation.
• Final Blocks: Final blocks are used for executing code at the end of the simulation. They are executed once all other processes in the simulation have completed.

Therefore, the main difference between initial and final blocks in SystemVerilog is the timing of their execution - initial blocks run at the beginning of the simulation, while final blocks run at the end.